Polysilicon germanium (poly-SiGe) is advantageous over polysilicon as a gate electrode material due to its reduced dopant diffusion properties and work function engineering capability. Consequently, poly-SiGe films have gained much attention for design and manufacturing of MOS devices.
Advances in semiconductor manufacturing technology have allowed integration of hundreds of millions of circuit elements, such as transistors, on a single integrated circuit (IC). In order to achieve such increases in density, interconnect line widths become smaller and overall dimensions of metal-oxide-semiconductor field effect transistors (MOSFETs) have decreased. These transistor devices are commonly referred to as FETs, and will thus be so referred to herein.
Transistor scaling typically involves more than just a linear reduction of a width and length of the FET. For example, both source/drain (S/D) junction depth and gate insulator thickness are also typically reduced in order to produce a FET with the desired electrical characteristics. As device geometries continue to scale downward, issues involving dopant diffusion have become a significant engineering challenge. Among these challenges is limiting effects related to gate depletion and dopant penetration of a thin gate dielectric. Gate depletion and dopant penetration lead to device performance issues related to changes in threshold voltage or turn-on voltage of a transistor and also relate to sub-threshold leakage current or inability to completely turn the transistor off. In PMOSFETs, the dopant penetration will shift the threshold voltage from negative to positive, making it difficult or impossible to turn the transistor off. In NMOSFETs, the opposite will occur.
Doped polysilicon is typically used as the gate material of most FET devices. Since doped polysilicon is a semiconductive material, the polysilicon tends to experience formation of a depletion region adjacent to the interface between a gate electrode and a gate insulator (also referred to as the gate dielectric) when a voltage is applied to the gate electrode. Another cause of the depletion region is an inability of ion implantation and subsequent thermal anneal process steps to result in a homogeneously doped layer from top to bottom. As transistor scaling has substantially reduced a thickness of the gate insulator layer, a width of the depletion region in the doped polysilicon gate electrode has come to play a more significant role in determining the electrical characteristics of the FET. Unfortunately, any occurrence of a depletion region in the gate electrode tends to degrade transistor performance.
Transistor scaling has also reduced a thickness of the gate dielectric layer. The gate dielectric layer separates the gate electrode from an underlying substrate or gate channel. A reduction in thickness of the gate dielectric makes the device more sensitive to issues of dopant penetration from the gate electrode across the gate dielectric. The dopant penetration also causes device performance degradation related to changes in both threshold voltage and sub-threshold leakage.
U.S. Pat. No. 6,373,112 to Murthy et al., entitled “Polysilicon-Germanium MOSFET Gate Electrodes,” describes an insulated gate field effect transistor (FET) of a particular conductivity type, with a gate electrode including a polycrystalline SiGe layer. Murthy et al. describes a process that includes forming ultra-thin silicon seed film superjacent a gate dielectric layer followed by forming a SiGe layer over the seed layer. The thin Si seed layer enables deposition of the SiGe film to be substantially uniform and continuous without significant gate oxide degradation. The small thickness of the seed layer also enables effective Ge diffusion into the Si seed layer during subsequent deposition and/or subsequent thermal operations, resulting in a homogenous Ge concentration in the seed film and the SiGe overlayer.
Further, the polysilicon germanium gate electrode is gaining attention for MOS transistors due to its material properties of reduced dopant diffusion, enhanced carrier mobility, and tunable work function. As gate dielectric layers are reduced in thickness, the gate capacitance is increased. Therefore, the capacitance due to the gate depletion effect becomes more dominant because it is smaller than the gate capacitance and the two capacitive regions are in series. This is due to the relation for effective capacitance
      C    eff    =                    C        gate            ·              C        depletion                            C        gate            +              C        depletion            
To minimize an effect of gate depletion, the dopant distribution should be kept as uniform as possible throughout the layer. Additionally, the dopant should not be allowed to penetrate into the gate dielectric layer.
However, problems of gate depletion and gate penetration are still not completely resolved by the addition of Ge to the polysilicon layer. The gate depletion problem still exists due to inhomogeneous doping throughout the poly layers as a result of an ion implantation profile, as well as the gate penetration problem associated with ion implantation straggle.
Therefore, what is needed is a gate electrode structure that substantially overcomes the problems associated with gate depletion and methods of making such a gate electrode structure.